A) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of doping boron (B) shallowly and at a high concentration and a semiconductor device manufactured by this method.
B) Description of the Related Art
As transistors are miniaturized and become microfine, it becomes necessary to make shallow a junction depth of source/drain regions in order to suppress the short channel effects. Extension regions having a shallow junction depth are formed on both sides of the gate electrode, sandwiching the channel region, and deep source/drain regions are formed at positions spaced from the gate electrode. As a gate electrode length becomes short, an effective gate length becomes shorter than an actual gate length, and a phenomenon of a lowered threshold value occurs.
In order to ensure a desired threshold value and form shallow and low resistance extension regions, pocket (halo) regions are formed surrounding the extension regions, impurities (dopant) of a conductivity type opposite to that of the extension regions being doped in the pocket regions. Ion implantation for forming the pocket regions is performed along a plurality of directions, e.g., along the directions tilted by about 30° from a substrate normal direction.
Ion implantation is used for adding dopant. Implanted dopant is initially electrically non-active, and damages are formed in ion implanted semiconductor. In order to activate dopant and restore (recrystallize) the damaged semiconductor, annealing such as rapid thermal annealing (RTA) using a halogen lamp is performed.
It is essential to reduce parasitic resistance of the extension regions of source/drain regions in order to realize a miniaturized and high performance transistor. To this end, it is required to form extension regions which are shallow and have low resistance and a steep dopant profile. High temperature annealing is necessary for activating dopant highly efficiently. In order to realize a steep dopant profile, it is necessary to suppress dopant diffusion.
It is desired to perform annealing which has a high arrival or reach temperature to realize highly efficient activation of dopant and has a short high temperature stay time to suppress dopant diffusion. From this reason, spike annealing has been used which is RTA having a very short highest temperature stay time. Spike annealing can realize 0 second of the highest temperature Tmax stay time. However, a stay time at a temperature 50° C. lower than the peak temperature Tmax (Tmax−50° C.) or above is about 1 to 2 sec, so that thermal diffusion of dopant occurs.
If a shallow junction is to be formed by suppressing diffusion of dopant, it is necessary to lower an annealing temperature. However, a dopant activation factor lowers and a sheet resistance increases. As the annealing temperature is raised to increase the activation factor, dopant is diffused and the junction becomes deep. As described above, it is difficult for conventional spike annealing to form a shallow and low resistance diffusion layer required by miniaturized transistors. Further, spike annealing is accompanied by diffusion of increased speed (abnormal diffusion) at the initial annealing stage ascribed to damages formed during ion implantation, which makes it more difficult to form a shallow junction.
JP-A-2004-235603 proposes to dope one of diffusion suppressing substances N, Ar, F and C, most preferably N, during impurity ion implantation for pocket regions, in order to make a steep dopant concentration profile. Indium (In) is doped in an n-channel transistor to form p-type pocket regions. In order to form n-type pocket regions in a p-channel transistor, for example, antimony (Sb) is doped. For ion implantation for pocket regions, the diffusion suppressing substance N is doped. After ion implantation for extension regions and deep source/drain regions, spike annealing of almost 0 sec is performed. Since N is doped, leak current reduces. It is reported that a profile of the diffusion suppressing substance after annealing shows a peak at both positions at the surface and an interface between amorphous (A) and crystal (C) (A/C interface).
JP-A-2005-136382 proposes optical pulse annealing using an Xe flash lamp, instead of rapid thermal annealing (RTA) using a halogen lamp. An Xe flash lamp can irradiate an optical energy of 5 J/cm2 to 100 J/cm2 in about 0.1 msec to several hundred msec, and can raise a temperature to 900° C. to 1400° C. An Xe flash lamp can raise a temperature from 450° C. to 1300° C. in about 3 msec, and from 900° C. to 1300° C. in about 1 msec. This proposal reports that a dopant activation rate or factor is insufficient at a temperature lower than 900° C. and dopant diffusion becomes remarkable at a temperature higher than 1400° C. Annealing with an annealing time of a msec order is called msec annealing.
In this proposal, a dummy gate is formed and extensions and deep source/drain regions are formed, and thereafter the dummy gate is removed and channel doping is executed to provide the function similar to that of pocket regions. The proposal reports that although In doped by the channel doping was able to be activated only by about 20% by RTA with halogen lamp, In was able to be activated by about 80% by msec annealing using a flash lamp. This proposal also teaches that
since msec annealing after the last channel doping activates impurities in the other regions, RTA may be performed at 500° C. to 900° C. after preceding ion implantation for the extensions and source/drain regions to suppress diffusion to 5 nm or less and recrystallize damaged semiconductor, instead of performing msec annealing each time dopant is implanted.
JP-A-2005-142344 indicates that it is necessary to activate impurities after ion implantation and recrystallize an amorphousized layer, and teaches to combine flash lamp annealing (FLA) not diffusing impurities and reducing crystal defects and FLA activating impurities, and perform this combined annealing after impurity ions are implanted. For example, first FLA is executed at a preheating of 400° C. and a radiation energy density of 24 J/cm2, and second FLA is executed at a preheating of 450° C. and a radiation energy density of 28 J/cm2. This publication also teaches that RTA may be executed in place of first FLA and that if ion implantation is to be executed a plurality of times, although FLA activating impurities is executed after the last impurity implantation, the FLA may be omitted after the preceding impurity implantation processes.
There is also a proposal of msec annealing using laser in place of an Xe flash lamp. Ultratech Inc., CA., U.S.A. sells a msec annealing system LSA100 using continuous wave (CW) laser. The specification describes that a temperature can be raised or lowered in a psec order to in a msec order by scanning the surface of a silicon substrate with a laser beam.
With the advent of such flash lamp annealing and laser annealing, msec annealing technologies have been provided which can raise a temperature higher than 1200 to 1300° C. in a ultra short time of about 1 msec. As a heating time is shortened, diffusion of dopant can be suppressed, and as an arrival or reach temperature is raised, a dopant activation rate or factor can be improved.